1. Field of the Invention
The invention relates to a semiconductor package substrate and, more particularly, to a semiconductor package substrate that supports a semiconductor chip when the semiconductor chip is being packaged.
2. Description of the Related Art
In the field of semiconductor packaging technique, because the semiconductor integration has been dynamically enhanced, and because the design of semiconductor chips has been developed in the direction of function integration, many products of system on chip (SOC) then have been introduced one by one. At the same time, by strengthening the data calculation processing ability of semiconductor products, the demand of I/O pads, which are indispensable on semiconductor chips, has relatively been increased. Therefore, the technique of semiconductor packaging must be in accord with the requirements of semiconductor development.
In recent years, due to fast development of very large scale integration (VLSI) technology or even ultra large scale integration (ULSI) technology, the semiconductor packaging products and techniques that are of high density and of high pin count have been relatively enhanced. That is, the demand for the contact number of the semiconductor package substrate has been gradually increasing, and correspondingly, the density and the area of wiring on the semiconductor package substrate have been increased as well. However, along with the increase in the operating frequency of integrated circuits, the problem with the adjacent signals interfering with one another on the transmitting path becomes more obvious. Therefore, providing shielding pads among the signal pads that are used for transmitting signals are required in order to separate adjacent signal pads thereby reducing the cross-talk among the adjacent signals.
As shown in FIG. 1, the conventional semiconductor package substrate includes a substrate 11, a chip contact area 12, an inner pad portion 13 and an outer pad portion 14. In the conventional semiconductor package substrate, the chip contact area 12 is formed in the center of one side of substrate 11, the inner pad portion 13 is formed on one side of substrate 11 and locates on the periphery of the chip contact area 12, and the outer pad portion 14 is formed on the periphery of the inner pad 13. Each of the outer pad portion 14 and the inner pad 13 includes a plurality of signal pads 15 and a plurality of shielding pads 16, as shown in FIG. 2. The signal pads 15 are electrically connected to the die pads of a semiconductor chip separately by wire bonding. In addition, the signal pads 15 and the shielding pads 16, each through a plurality of via holes 17 that are formed in the substrate 11, are electrically connected to the solder balls that are formed on the other side of the substrate 11. The signal pads 15 input signals to or output signals from external devices through the solder balls, while the shielding pads 16 protect the adjacent signal pads 15 thereof by grounding the solder balls, which prevents adjacent signals from interfering with one another when the signals are transmitted on each of the signal pads 15.
However, because providing the via holes 17 on each of the shielding pads 16 is a must, a large portion of the area of the semiconductor package substrate is occupied by the via holes 17, especially the area on the periphery of the inner pad 13, which has only very limited area for use. Consequently, the existence of the via holes 17 limits the quantity of signal pads 15 and shielding pads 16 that can be provided.
To sum up, since the area on the surface of the semiconductor package substrate is limited, and since the indispensable via holes must occupy a large portion of the area, it is an important task for the current package technique to provide a semiconductor package substrate that can reduce the quantity of via holes formed on the limited area, thereby increasing the quantity of the signal pads and the shielding pads.